Search - full adder

[WEB Code] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL - sequence
Platform: | Size: 15972 | Author: 李成 | Hits:

[Goverment application] ex15

Description: 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
Platform: | Size: 6144 | Author: 杨川 | Hits:

[Linux-Unix] cadence_multi-threshold

Description: linux下(fedora版本)的cadence中编译4位全加器的实现, 在不同的阈值电压调解下观察点路的总体power和速度,以及逻辑的正确性. 可能会用到NCSU的FREEPDF工具包-this is a package of three projects, low-vth, high-vth, and optimum architecture vth four bit full adder design. In the environment of Cadence and then simulated in Hspice and linked to VIVA at last we use the nanosim.
Platform: | Size: 4353024 | Author: ququmo | Hits:

[matlab] quanjiaqi

Description: 建立了基于matlab语言的四位全加器仿真模型，通过了系统验证。-Matlab language is established based on four full adder simulation model, verified by the system.
Platform: | Size: 4096 | Author: ZHANGCHUN | Hits:

[VHDL-FPGA-Verilog] adder_fa4bit

Description: 4 bit full adder verilog code n test bench
Platform: | Size: 27648 | Author: M. Usman | Hits:

[VHDL-FPGA-Verilog] Full.adder

Description: Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] Full-Adder

Description: Full Adder to add 4 bits of input
Platform: | Size: 1024 | Author: med7at2010 | Hits:

[VHDL-FPGA-Verilog] 4bit-adder_verilog

Description: 4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
Platform: | Size: 40960 | Author: d | Hits:

[VHDL-FPGA-Verilog] four_bit-full-adder

Description: 四位的全加器，包含8421码与2421码的相互转换，2421码的加法修正-Four of the full adder, including 8421 yards and 2421 yards of the conversion, the addition of amendments to 2421 yards
Platform: | Size: 76800 | Author: 孙晟轩 | Hits:

[Other] Full-Adder

Description: 用VHDL实现的全加器，采用dataflow style编写，是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner（Testbench included）
Platform: | Size: 1024 | Author: chenzhang | Hits:

[VHDL-FPGA-Verilog] Four-bit-full-adder

Description: 四位全加器，是自己编写的，如有错误，请原谅-I have written four full adder, is subject to error, please forgive
Platform: | Size: 39936 | Author: 王子 | Hits:

[VHDL-FPGA-Verilog] 16-bit-binary-full-adder

Description: 16位二进制全加器，带最高位的进位，主要用QUARTUS仿真工具实现-16-bit binary full adder
Platform: | Size: 1024 | Author: peter | Hits:

[VHDL-FPGA-Verilog] VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling.z

Description: VHDL Code For Full Adder By Data Flow Modelling
Platform: | Size: 32768 | Author: rik | Hits:

[VHDL-FPGA-Verilog] ANALYSIS-OF-FULL-ADDER

Description: DESCRIPTION OF FULL ADDER
Platform: | Size: 3072 | Author: nirali | Hits:

[Other] Design-of-full-adder

Description: 熟悉VHDL元件例化语句的作用熟悉全加器的工作原理用VHDL语言设计一位二进制全加器，并仿真。-The role of components instantiated. Familiar with VHDL statements Familiar with the working principle of full adder Using VHDL language to design a binary full adder, and simulation.
Platform: | Size: 9216 | Author: 王程序 | Hits:

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